In digital signal processing, it is common to drive a single data bus with a plurality of independent integrated circuits ("ICs"). Each IC may provide an output signal to the data bus for further signal processing. However, it is often desirable to disable or power-down one or more of the ICs while others connected to the data bus remain active. The active ICs continue to provide output signals to the data bus. Accordingly, the disabled ICs must be constructed such that they do not load the output signals on the data bus provided by those ICs which still remain active. Typically, a driver circuit is included within the IC to serve this non-loading purpose.
Non-loading CMOS IC drivers available today typically use N channel transistors in an open drain configuration to drive the output signal. The use of an N channel transistor requires an additional pullup resistor external to the IC associated with the transistor and its supply voltage signal V.sub.cc. The pullup resistor combined with capacitance along the data bus can give rise to power consumption and delay time in output signal transitions. The power consumption arises from current through the pullup resistor when the transistor output is a logic "0". The delay arises from the slow logic "0" to logic "1" transition and is determined by the R-C time constant associated with the pullup resistor and circuit capacitance. The resistance value may be lessened in order to decrease delay times associated therewith, but this will correspondingly increase power consumption. Alternatively, the resistance may be increased to minimize power consumption, but this will increase delay times associated with the output signal.
Therefore, a need has arisen for an output driver circuit which may be utilized with an IC driving a data bus, wherein the data bus may remain active while the IC is powered down. Further, this output driver should minimize power consumption and delay problems associated with the prior art.